/*
 *Copyright (c) 2024 Black Sesame Technologies
 *
 *Licensed under the Apache License, Version 2.0 (the "License");
 *you may not use this file except in compliance with the License.
 *You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 *Unless required by applicable law or agreed to in writing, software
 *distributed under the License is distributed on an "AS IS" BASIS,
 *WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 *See the License for the specific language governing permissions and
 *limitations under the License.
*/

#ifndef _R5_CLK_H
#define _R5_CLK_H

#include "../../common/RegBase.h"
#include "../../library/general_inc.h"
#include "../../library/utility_lite.h"

typedef unsigned int uint32_t;

enum{

    //safety clk

    st_main_clk_25m = 0,

    // sel1 1:0

    mux_clk_r5_1200m = 1,
    mux_clk_r5_1000m ,
    mux_clk_r5_600m ,

    // sel1 5:4
    mux_clk_r5_csr_clk_200m = 1,
    mux_clk_r5_csr_clk_125m ,
    mux_clk_r5_csr_clk_50m ,

    //sel1 6
    mux_clk_coresight_crm_clk_int_div = 1,

    //sel1 9:8
    mux_clk_safenoc_gaclk_clk_600m = 1,
    mux_clk_safenoc_gaclk_clk_300m ,
    mux_clk_safenoc_gaclk_clk_125m ,

    //sel1 11:10
    mux_clk_safenoc_hclk_clk_300m = 1,
    mux_clk_safenoc_hclk_clk_200m , 
    mux_clk_safenoc_hclk_clk_125m ,

    //sel1 13:12
    mux_clk_safenoc_pclk_clk_200m = 1,
    mux_clk_safenoc_pclk_clk_50m ,
    mux_clk_safenoc_pclk_clk_125m ,

    //sel2 1:0
    mux_clk_lsp0_adc_wclk_clk_500m = 1,
    mux_clk_lsp0_adc_wclk_clk_250m ,
    mux_clk_lsp0_adc_wclk_clk_125m ,

    //sel2 3:2
    mux_clk_sdma_gwclk_clk_400m = 1,
    mux_clk_sdma_gwclk_clk_300m ,
    mux_clk_sdma_gwclk_clk_250m ,

    //sel2 5:4
    mux_clk_sdma_ghclk_clk_200m = 1,
    mux_clk_sdma_ghclk_clk_100m ,
    mux_clk_sdma_ghclk_clk_125m ,

    //sel2 7:6
    mux_clk_sram_clk_600m = 1,
    mux_clk_sram_clk_400m ,
    mux_clk_sram_clk_250m ,

    //sel2 9:8
    mux_clk_qspi_clk_200m = 1,
    mux_clk_qspi_clk_400m ,
    mux_clk_qspi_clk_250m ,

    //sel2 13:12
    mux_clk_lsp0_wclk_clk_400m = 1,
    mux_clk_lsp0_wclk_clk_200m ,
    mux_clk_lsp0_wclk_clk_125m ,

    //sel2 15:14
    mux_clk_lsp0_pclk_clk_200m = 1,
    mux_clk_lsp0_pclk_clk_50m ,
    mux_clk_lsp0_pclk_clk_125m ,

    //sel2 17:16
    mux_clk_ssp_pclk_clk_200m = 1,
    mux_clk_ssp_pclk_clk_50m ,
    mux_clk_ssp_pclk_clk_125m ,

    //sel2 19:18
    mux_clk_gmac_mclk_lb_gamc_ptp_clk_125m = 0,
    mux_clk_gmac_mclk_lb_gamc_epp_rxclk_125m ,
    mux_clk_gmac_mclk_st_rgmii_rxclk_125m ,
    mux_clk_gmac_125m ,

    //sel2 20
    mux_clk_div_clk_gmac_ptp_clk = 1,


    //realtime 
    lb_rt_osc_clk_in_25m = 0,

    //rt-clk_sel1

    mux_clk_r5_2_axip_nic_clk_600m = 1,
    mux_clk_r5_2_axip_nic_clk_400m ,
    mux_clk_r5_2_axip_nic_clk_300m ,

    mux_clk_r5_1_axip_nic_clk_600m = 1,
    mux_clk_r5_1_axip_nic_clk_400m ,
    mux_clk_r5_1_axip_nic_clk_300m ,

    mux_clk_r5_0_axip_nic_clk_600m = 1,
    mux_clk_r5_0_axip_nic_clk_400m ,
    mux_clk_r5_0_axip_nic_clk_300m ,

    mux_clk_r5_2_axis_nic_clk_600m = 1,
    mux_clk_r5_2_axis_nic_clk_400m ,
    mux_clk_r5_2_axis_nic_clk_300m ,

    mux_clk_r5_1_axis_nic_clk_600m = 1,
    mux_clk_r5_1_axis_nic_clk_400m ,
    mux_clk_r5_1_axis_nic_clk_300m ,

    mux_clk_r5_0_axis_nic_clk_600m = 1,
    mux_clk_r5_0_axis_nic_clk_400m ,
    mux_clk_r5_0_axis_nic_clk_300m ,

    mux_clk_rtnoc_aclk_600m = 1,
    mux_clk_rtnoc_aclk_400m ,
    mux_clk_rtnoc_aclk_200m ,

    mux_clk_r5_2_1200m_1200m = 1,
    mux_clk_r5_2_1200m_1000m ,
    mux_clk_r5_2_1200m_600m  ,

    mux_clk_r5_1_1200m_1200m = 1,
    mux_clk_r5_1_1200m_1000m ,
    mux_clk_r5_1_1200m_600m  ,

    mux_clk_r5_0_1200m_1200m = 1,
    mux_clk_r5_0_1200m_1000m ,
    mux_clk_r5_0_1200m_600m  ,

    //rt-clk_sel2

    mux_clk_apb0_pclk_100m_100m = 1,
    mux_clk_apb0_pclk_100m_80m  ,
    mux_clk_apb0_pclk_100m_50m  ,

    mux_clk_sdma_nic2x1_hclk_400m = 1,
    mux_clk_sdma_nic2x1_hclk_200m ,
    mux_clk_sdma_nic2x1_hclk_100m ,

    mux_clk_lsp1_pclk_200m = 1,
    mux_clk_lsp1_pclk_100m ,
    mux_clk_lsp1_pclk_50m  ,

    mux_clk_lsp1_wclk_400m = 1,
    mux_clk_lsp1_wclk_100m ,
    mux_clk_lsp1_wclk_125m ,

    mux_clk_lsp0_pclk_200m = 1, 
    mux_clk_lsp0_pclk_100m ,
    mux_clk_lsp0_pclk_50m  ,

    mux_clk_lsp0_wclk_400m = 1,
    mux_clk_lsp0_wclk_100m ,
    mux_clk_lsp0_wclk_125m ,

    mux_clk_sdma0_pclk_200m_400m = 1,
    mux_clk_sdma0_pclk_200m_200m ,
    mux_clk_sdma0_pclk_200m_250m ,

    mux_clk_sram1_600m_600m = 1,
    mux_clk_sram1_600m_400m ,
    mux_clk_sram1_600m_250m ,

    mux_clk_sram0_600m_600m = 1,
    mux_clk_sram0_600m_400m ,
    mux_clk_sram0_600m_250m ,

    mux_clk_rtdma_400m_400m = 1,
    mux_clk_rtdma_400m_200m ,
    mux_clk_rtdma_400m_250m ,

    mux_clk_nic2x1_hclk_600m = 1,
    mux_clk_nic2x1_hclk_400m ,
    mux_clk_nic2x1_hclk_250m ,


    //switch
    lb_sw_osc_clk_in_25m = 0,

    //sw-clk sel0
    mux_clk_sw_epp_apb_clk_200m = 1,
    mux_clk_sw_epp_apb_clk_100m ,
    mux_clk_sw_epp_apb_clk_50m ,

    mux_clk_sw_epp_axi_clk_800m = 1,
    mux_clk_sw_epp_axi_clk_600m ,
    mux_clk_sw_epp_axi_clk_400 ,

    mux_clk_sw_gmac_apb_clk_200m = 1,
    mux_clk_sw_gmac_apb_clk_100m ,
    mux_clk_sw_gmac_apb_clk_50m ,

    mux_clk_sw_gmac_axi_clk_200m = 1,
    mux_clk_sw_gmac_axi_clk_100m ,
    mux_clk_sw_gmac_axi_clk_50m ,

    mux_clk_sw_r5_ppi2_clk_600m = 1,
    mux_clk_sw_r5_ppi2_clk_400m ,
    mux_clk_sw_r5_ppi2_clk_200m ,

    mux_clk_sw_r5_ppi1_clk_600m = 1,
    mux_clk_sw_r5_ppi1_clk_400m ,
    mux_clk_sw_r5_ppi1_clk_200m ,

    mux_clk_sw_r5_ppi0_clk_600m = 1,
    mux_clk_sw_r5_ppi0_clk_400m ,
    mux_clk_sw_r5_ppi0_clk_200m ,

    mux_clk_sw_r5_apb4_5_clk_200m = 1,
    mux_clk_sw_r5_apb4_5_clk_100m ,
    mux_clk_sw_r5_apb4_5_clk_50m ,

    mux_clk_sw_r5_apb2_3_clk_200m = 1,
    mux_clk_sw_r5_apb2_3_clk_100m ,
    mux_clk_sw_r5_apb2_3_clk_50m ,

    mux_clk_sw_r5_apb0_1_clk_200m = 1,
    mux_clk_sw_r5_apb0_1_clk_100m ,
    mux_clk_sw_r5_apb0_1_clk_50m ,

    mux_clk_sw_r5_nic4_5_clk_600m = 1,
    mux_clk_sw_r5_nic4_5_clk_400m ,
    mux_clk_sw_r5_nic4_5_clk_200m ,

    mux_clk_sw_r5_nic2_3_clk_600m = 1,
    mux_clk_sw_r5_nic2_3_clk_400m ,
    mux_clk_sw_r5_nic2_3_clk_200m ,

    mux_clk_sw_r5_nic0_1_clk_600m = 1,
    mux_clk_sw_r5_nic0_1_clk_400m ,
    mux_clk_sw_r5_nic0_1_clk_200m ,

    mux_clk_sw_r5_core4_5_clk_1200m = 1,
    mux_clk_sw_r5_core4_5_clk_800m ,
    mux_clk_sw_r5_core4_5_clk_400m ,

    mux_clk_sw_r5_core2_3_clk_1200m = 1,
    mux_clk_sw_r5_core2_3_clk_800m ,
    mux_clk_sw_r5_core2_3_clk_400m ,

    mux_clk_sw_r5_core0_1_clk_1200m = 1,
    mux_clk_sw_r5_core0_1_clk_800m ,
    mux_clk_sw_r5_core0_1_clk_400m ,

    //sw-clk sel1

    mux_clk_sw_sdma_axi_clk_400m = 1,
    mux_clk_sw_sdma_axi_clk_200m ,
    mux_clk_sw_sdma_axi_clk_100m ,

    mux_clk_sw_sdma_core_clk_400m = 1,
    mux_clk_sw_sdma_core_clk_200m ,
    mux_clk_sw_sdma_core_clk_100m ,

    mux_clk_sw_sdma_cfg_clk_200m = 1,
    mux_clk_sw_sdma_cfg_clk_100m ,
    mux_clk_sw_sdma_cfg_clk_50m ,

    mux_clk_sw_sysctrl_csr_clk_200m = 1,
    mux_clk_sw_sysctrl_csr_clk_100m ,
    mux_clk_sw_sysctrl_csr_clk_50m ,

    mux_clk_sw_flexray_ahb_nic_bridge_clk_400m = 1,
    mux_clk_sw_flexray_ahb_nic_bridge_clk_200m ,
    mux_clk_sw_flexray_ahb_nic_bridge_clk_100m ,

    mux_clk_sw_standby_sram_clk_200m = 1,
    mux_clk_sw_standby_sram_clk_100m ,
    mux_clk_sw_standby_sram_clk_50m ,

    mux_clk_sw_sram1_clk_600m = 1,
    mux_clk_sw_sram1_clk_400m ,
    mux_clk_sw_sram1_clk_200m ,

    mux_clk_sw_sram0_clk_600m = 1,
    mux_clk_sw_sram0_clk_400m ,
    mux_clk_sw_sram0_clk_200m ,

    mux_clk_sw_dma_clk_400m = 1,
    mux_clk_sw_dma_clk_200m ,
    mux_clk_sw_dma_clk_100m ,

    mux_clk_sw_security_acceleration_clk_600m = 1,
    mux_clk_sw_security_acceleration_clk_400m ,
    mux_clk_sw_security_acceleration_clk_200m ,

    mux_clk_sw_security_acceleration_axi_clk_600m = 1,
    mux_clk_sw_security_acceleration_axi_clk_400m ,
    mux_clk_sw_security_acceleration_axi_clk_200m ,

    mux_clk_sw_lsp_flexray_ahb_clk_200m = 1,
    mux_clk_sw_lsp_flexray_ahb_clk_100m ,
    mux_clk_sw_lsp_flexray_ahb_clk_50m ,

    mux_clk_sw_lsp_can_work_clk_400m = 1,
    mux_clk_sw_lsp_can_work_clk_200m ,
    mux_clk_sw_lsp_can_work_clk_100m ,

    mux_clk_sw_lsp_work_clk_200m = 1,
    mux_clk_sw_lsp_work_clk_100m ,
    mux_clk_sw_lsp_work_clk_50m ,

    mux_clk_sw_lsp_can_apb_clk_600m = 1,
    mux_clk_sw_lsp_can_apb_clk_400m ,
    mux_clk_sw_lsp_can_apb_clk_200m ,

    mux_clk_sw_lsp_pcs_apb_clk_200m = 1,
    mux_clk_sw_lsp_pcs_apb_clk_100m ,
    mux_clk_sw_lsp_pcs_apb_clk_50m ,

    //sw-clk sel2

    mux_clk_sw_ptp_clk_sel_ptp_div_clk = 1,

    mux_clk_sw_ptp_clk_sel_ptp_div_clk_ptp_mux_clk = 0,
    mux_clk_sw_ptp_clk_sel_ptp_div_clk_ptp_mux_clk_2 ,
    mux_clk_sw_ptp_clk_sel_ptp_div_clk_ptp_mux_clk_4 ,
    mux_clk_sw_ptp_clk_sel_ptp_div_clk_ptp_mux_clk_5 ,

    mux_clk_sw_ptp_clk_sel_ptp_mux_clk_input_clk_pad_ptp_clk = 0,
    mux_clk_sw_ptp_clk_sel_ptp_mux_clk_external_portx = 8 ,
    mux_clk_sw_ptp_clk_sel_ptp_mux_clk_pll_eth_125m = 0xe ,
    mux_clk_sw_ptp_clk_sel_ptp_mux_clk_external_gmac_recv_clk = 0xf,

    apbsw_clk_sel_200m = 1,
    apbsw_clk_sel_100m ,
    apbsw_clk_sel_50m ,

    noc_clk_sel_600m = 1,
    noc_clk_sel_400m ,
    noc_clk_sel_200m ,

    crm_clk_sel_200m = 1,
    crm_clk_sel_100m ,
    crm_clk_sel_50m ,



};









#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_SAFENOC_PCLK_MASK                                   (0x00003000UL) /*0 : st_main_clk 1 : clk _200m 2 : clk_50m 3 : clk_125m*/
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_SAFENOC_PCLK_SHIFT                                  (12U)
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_SAFENOC_PCLK(x)                                     (((uint32_t)(((uint32_t)(x)) << SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_SAFENOC_PCLK_SHIFT)) & SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_SAFENOC_PCLK_MASK)

#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_SAFENOC_HCLK_MASK                                   (0x00000C00UL) /*0 : st_main_clk 1 : clk _300m 2 : clk_200m 3 : clk_125m*/
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_SAFENOC_HCLK_SHIFT                                  (10U)
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_SAFENOC_HCLK(x)                                     (((uint32_t)(((uint32_t)(x)) << SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_SAFENOC_HCLK_SHIFT)) & SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_SAFENOC_HCLK_MASK)

#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_SAFENOC_ACLK_MASK                                   (0x00000300UL) /*0 : st_main_clk 1 : clk _600m 2 : clk_300m 3 : clk_125m*/
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_SAFENOC_ACLK_SHIFT                                  (8U)
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_SAFENOC_ACLK(x)                                     (((uint32_t)(((uint32_t)(x)) << SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_SAFENOC_ACLK_SHIFT)) & SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_SAFENOC_ACLK_MASK)

#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CORESIGHT_CRM_CLK_MASK                                  (0x00000040UL) /*0:st_main_clk 1: int_div*/
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CORESIGHT_CRM_CLK_SHIFT                                 (6U)
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CORESIGHT_CRM_CLK(x)                                    (((uint32_t)(((uint32_t)(x)) << SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CORESIGHT_CRM_CLK_SHIFT)) & SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CORESIGHT_CRM_CLK_MASK)

#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_R5_CSR_CLK_MASK                                     (0x00000030UL) /*0 : st_main_clk 1 : clk _200m 2 : clk_125m 3 : clk_50m*/
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_R5_CSR_CLK_SHIFT                                    (4U)
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_R5_CSR_CLK(x)                                       (((uint32_t)(((uint32_t)(x)) << SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_R5_CSR_CLK_SHIFT)) & SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_R5_CSR_CLK_MASK)

#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_R5_MASK                                             (0x00000003UL) /*0 : st_main_clk 1 : clk _1200m 2 : clk_1000m 3 : clk_600m*/
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_R5_SHIFT                                            (0U)
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_R5(x)                                               (((uint32_t)(((uint32_t)(x)) << SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_R5_SHIFT)) & SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL1_CONFIG_MUX_CLK_R5_MASK)



#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SGMAC_PTP_CLK_MASK                                  (0x00100000UL) /*0 : st_main_clk 1 : div_clk_gamc_ptp_clk*/
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SGMAC_PTP_CLK_SHIFT                                 (20U)
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SGMAC_PTP_CLK(x)                                    (((uint32_t)(((uint32_t)(x)) << SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SGMAC_PTP_CLK_SHIFT)) & SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SGMAC_PTP_CLK_MASK)

#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_GAMC_MCLK_MASK                                      (0x000C0000UL) /*0 : lb_gmac_ptp_clk_125m 1 : lb_gmac_epp_rxclk_125m 2 : lb_gmac_se_rgmii_rxclk_125m 3 : clk_125m*/
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_GAMC_MCLK_SHIFT                                     (18U)
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_GAMC_MCLK(x)                                        (((uint32_t)(((uint32_t)(x)) << SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_GAMC_MCLK_SHIFT)) & SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_GAMC_MCLK_MASK)

#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SSP_PCLK_MASK                                       (0x00030000UL) /*0 : st_main_clk 1 : clk_200m 2 : clk_50m 3 : clk_125m*/
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SSP_PCLK_SHIFT                                      (16U)
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SSP_PCLK(x)                                         (((uint32_t)(((uint32_t)(x)) << SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SSP_PCLK_SHIFT)) & SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SSP_PCLK_MASK)

#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_LSP0_PCLK_MASK                                      (0x0000C000UL) /*0 : st_main_clk 1 : clk_200m 2 : clk_50m 3 : clk_125m*/
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_LSP0_PCLK_SHIFT                                     (14U)
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_LSP0_PCLK(x)                                        (((uint32_t)(((uint32_t)(x)) << SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_LSP0_PCLK_SHIFT)) & SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_LSP0_PCLK_MASK)

#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_LSP0_WCLK_MASK                                      (0x00003000UL) /*0 : st_main_clk 1 : clk _400m 2 : clk_200m 3 : clk_125m*/
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_LSP0_WCLK_SHIFT                                     (12U)
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_LSP0_WCLK(x)                                        (((uint32_t)(((uint32_t)(x)) << SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_LSP0_WCLK_SHIFT)) & SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_LSP0_WCLK_MASK)

#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_QSPI_200M_MASK                                      (0x00000300UL) /*0 : st_main_clk 1 : clk_200m 2 : clk_400m 3 : clk_250m*/
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_QSPI_200M_SHIFT                                     (8U)
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_QSPI_200M(x)                                        (((uint32_t)(((uint32_t)(x)) << SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_QSPI_200M_SHIFT)) & SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_QSPI_200M_MASK)

#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SRAM_600M_MASK                                      (0x000000C0UL) /*0 : st_main_clk 1 : clk _600m 2 : clk_400m 3 : clk_250m*/
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SRAM_600M_SHIFT                                     (6U)
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SRAM_600M(x)                                        (((uint32_t)(((uint32_t)(x)) << SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SRAM_600M_SHIFT)) & SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SRAM_600M_MASK)

#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SDMA_200M_MASK                                      (0x00000030UL) /*0 : st_main_clk 1 : clk_200m 2 : clk_100m 3 : clk_125m*/
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SDMA_200M_SHIFT                                     (4U)
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SDMA_200M(x)                                        (((uint32_t)(((uint32_t)(x)) << SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SDMA_200M_SHIFT)) & SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SDMA_200M_MASK)

#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SDMA_400M_MASK                                      (0x0000000CUL) /*0 : st_main_clk 1 : clk_400m 2 : clk_300m 3 : clk_250m*/
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SDMA_400M_SHIFT                                     (2U)
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SDMA_400M(x)                                        (((uint32_t)(((uint32_t)(x)) << SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SDMA_400M_SHIFT)) & SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_SDMA_400M_MASK)

#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_LSP0_ADC_WCLK_MASK                                  (0x00000003UL) /*0 : st_main_clk 1 : clk _500m 2 : clk_250m 3 : clk_125m*/
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_LSP0_ADC_WCLK_SHIFT                                 (0U)
#define SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_LSP0_ADC_WCLK(x)                                    (((uint32_t)(((uint32_t)(x)) << SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_LSP0_ADC_WCLK_SHIFT)) & SEC_SAFE_CRM_CSR_SAFETY_CLK_SEL2_CONFIG_MUX_CLK_LSP0_ADC_WCLK_MASK)




//realtime

#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_2_AXIP_NIC_CLK_MASK                                               (0x00300000UL) /*0:lb_rt_osc_clk_in(25m) 1:clk_600m 2:clk_400m 3:clk_300m*/
#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_2_AXIP_NIC_CLK_SHIFT                                              (20U)
#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_2_AXIP_NIC_CLK(x)                                                 (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_2_AXIP_NIC_CLK_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_2_AXIP_NIC_CLK_MASK)

#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_1_AXIP_NIC_CLK_MASK                                               (0x000C0000UL) /*0:lb_rt_osc_clk_in(25m) 1:clk_600m 2:clk_400m 3:clk_300m*/
#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_1_AXIP_NIC_CLK_SHIFT                                              (18U)
#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_1_AXIP_NIC_CLK(x)                                                 (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_1_AXIP_NIC_CLK_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_1_AXIP_NIC_CLK_MASK)

#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_0_AXIP_NIC_CLK_MASK                                               (0x00030000UL) /*0:lb_rt_osc_clk_in(25m) 1:clk_600m 2:clk_400m 3:clk_300m*/
#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_0_AXIP_NIC_CLK_SHIFT                                              (16U)
#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_0_AXIP_NIC_CLK(x)                                                 (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_0_AXIP_NIC_CLK_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_0_AXIP_NIC_CLK_MASK)

#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_2_AXIS_NIC_CLK_MASK                                               (0x0000C000UL) /*0:lb_rt_osc_clk_in(25m) 1:clk_600m 2:clk_400m 3:clk_300m*/
#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_2_AXIS_NIC_CLK_SHIFT                                              (14U)
#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_2_AXIS_NIC_CLK(x)                                                 (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_2_AXIS_NIC_CLK_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_2_AXIS_NIC_CLK_MASK)

#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_1_AXIS_NIC_CLK_MASK                                               (0x00003000UL) /*0:lb_rt_osc_clk_in(25m) 1:clk_600m 2:clk_400m 3:clk_300m*/
#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_1_AXIS_NIC_CLK_SHIFT                                              (12U)
#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_1_AXIS_NIC_CLK(x)                                                 (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_1_AXIS_NIC_CLK_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_1_AXIS_NIC_CLK_MASK)

#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_0_AXIS_NIC_CLK_MASK                                               (0x00000C00UL) /*0:lb_rt_osc_clk_in(25m) 1:clk_600m 2:clk_400m 3:clk_300m*/
#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_0_AXIS_NIC_CLK_SHIFT                                              (10U)
#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_0_AXIS_NIC_CLK(x)                                                 (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_0_AXIS_NIC_CLK_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_0_AXIS_NIC_CLK_MASK)

#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_RTNOC_ACLK_MASK                                                      (0x00000300UL) /*0:lb_rt_osc_clk_in(25m) 1:clk_600m 2:clk_400m 3:clk_200m*/
#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_RTNOC_ACLK_SHIFT                                                     (8U)
#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_RTNOC_ACLK(x)                                                        (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_RTNOC_ACLK_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_RTNOC_ACLK_MASK)

#define RT_CRM_CSR_RT_CLK_SEL1_RESERVED_MASK                                                                (0x000000C0UL) /*None*/
#define RT_CRM_CSR_RT_CLK_SEL1_RESERVED_SHIFT                                                               (6U)
#define RT_CRM_CSR_RT_CLK_SEL1_RESERVED(x)                                                                  (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL1_RESERVED_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL1_RESERVED_MASK)

#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_2_1200M_MASK                                                      (0x00000030UL) /*0:lb_rt_osc_clk_in(25m) 1:clk_1200m 2:clk_1000m 3:clk_600m*/
#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_2_1200M_SHIFT                                                     (4U)
#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_2_1200M(x)                                                        (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_2_1200M_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_2_1200M_MASK)

#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_1_1200M_MASK                                                      (0x0000000CUL) /*0:lb_rt_osc_clk_in(25m) 1:clk_1200m 2:clk_1000m 3:clk_600m*/
#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_1_1200M_SHIFT                                                     (2U)
#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_1_1200M(x)                                                        (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_1_1200M_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_1_1200M_MASK)

#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_0_1200M_MASK                                                      (0x00000003UL) /*0:lb_rt_osc_clk_in(25m) 1:clk_1200m 2:clk_1000m 3:clk_600m*/
#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_0_1200M_SHIFT                                                     (0U)
#define RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_0_1200M(x)                                                        (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_0_1200M_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL1_MUX_CLK_R5_0_1200M_MASK)


#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_APB0_PCLK_100M_MASK                                                  (0x0C000000UL) /*0:lb_rt_osc_clk_in(25m) 1:clk_100m 2:clk_80m 3:clk_50m*/
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_APB0_PCLK_100M_SHIFT                                                 (26U)
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_APB0_PCLK_100M(x)                                                    (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_APB0_PCLK_100M_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_APB0_PCLK_100M_MASK)

#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA1_PCLK_200M_MASK                                                 (0x03000000UL) /*It's been deleted, reserved*/
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA1_PCLK_200M_SHIFT                                                (24U)
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA1_PCLK_200M(x)                                                   (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA1_PCLK_200M_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA1_PCLK_200M_MASK)

#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA1_WCLK_200M_MASK                                                 (0x00C00000UL) /*It's been deleted, reserved*/
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA1_WCLK_200M_SHIFT                                                (22U)
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA1_WCLK_200M(x)                                                   (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA1_WCLK_200M_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA1_WCLK_200M_MASK)

#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA_NIC2X1_HCLK_MASK                                                (0x00300000UL) /*0:lb_rt_osc_clk_in(25m) 1:clk_400m 2:clk_200m 3:clk_100m*/
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA_NIC2X1_HCLK_SHIFT                                               (20U)
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA_NIC2X1_HCLK(x)                                                  (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA_NIC2X1_HCLK_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA_NIC2X1_HCLK_MASK)

#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP1_PCLK_MASK                                                       (0x000C0000UL) /*0:lb_rt_osc_clk_in(25m) 1:clk_200m 2:clk_100m 3:clk_50m*/
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP1_PCLK_SHIFT                                                      (18U)
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP1_PCLK(x)                                                         (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP1_PCLK_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP1_PCLK_MASK)

#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP1_WCLK_MASK                                                       (0x00030000UL) /*0:lb_rt_osc_clk_in(25m) 1:clk_400m 2:clk_100m 3:clk_125m*/
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP1_WCLK_SHIFT                                                      (16U)
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP1_WCLK(x)                                                         (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP1_WCLK_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP1_WCLK_MASK)

#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP0_PCLK_MASK                                                       (0x0000C000UL) /*0:lb_rt_osc_clk_in(25m) 1:clk_200m 2:clk_100m 3:clk_50m*/
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP0_PCLK_SHIFT                                                      (14U)
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP0_PCLK(x)                                                         (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP0_PCLK_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP0_PCLK_MASK)

#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP0_WCLK_MASK                                                       (0x00003000UL) /*0:lb_rt_osc_clk_in(25m) 1:clk_400m 2:clk_100m 3:clk_125m*/
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP0_WCLK_SHIFT                                                      (12U)
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP0_WCLK(x)                                                         (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP0_WCLK_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_LSP0_WCLK_MASK)

#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA0_PCLK_200M_MASK                                                 (0x00000C00UL) /*0:lb_rt_osc_clk_in(25m) 1:clk_400m 2:clk_200m 3:clk_250m*/
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA0_PCLK_200M_SHIFT                                                (10U)
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA0_PCLK_200M(x)                                                   (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA0_PCLK_200M_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA0_PCLK_200M_MASK)

#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SRAM1_600M_MASK                                                      (0x00000300UL) /*0:lb_rt_osc_clk_in(25m) 1:clk_600m 2:clk_400m 3:clk_250m*/
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SRAM1_600M_SHIFT                                                     (8U)
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SRAM1_600M(x)                                                        (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SRAM1_600M_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SRAM1_600M_MASK)

#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SRAM0_600M_MASK                                                      (0x000000C0UL) /*0:lb_rt_osc_clk_in(25m) 1:clk_600m 2:clk_400m 3:clk_250m*/
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SRAM0_600M_SHIFT                                                     (6U)
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SRAM0_600M(x)                                                        (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SRAM0_600M_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SRAM0_600M_MASK)

#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA0_WCLK_200M_MASK                                                 (0x00000030UL) /*It's been deleted, reserved*/
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA0_WCLK_200M_SHIFT                                                (4U)
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA0_WCLK_200M(x)                                                   (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA0_WCLK_200M_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_SDMA0_WCLK_200M_MASK)

#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_RTDMA_400M_MASK                                                      (0x0000000CUL) /*0:lb_rt_osc_clk_in(25m) 1:clk_400m 2:clk_200m 3:clk_250m*/
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_RTDMA_400M_SHIFT                                                     (2U)
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_RTDMA_400M(x)                                                        (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_RTDMA_400M_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_RTDMA_400M_MASK)

#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_NIC2X1_HCLK_MASK                                                     (0x00000003UL) /*0:lb_rt_osc_clk_in(25m) 1:clk_600m 2:clk_400m 3:clk_250m*/
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_NIC2X1_HCLK_SHIFT                                                    (0U)
#define RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_NIC2X1_HCLK(x)                                                       (((uint32_t)(((uint32_t)(x)) << RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_NIC2X1_HCLK_SHIFT)) & RT_CRM_CSR_RT_CLK_SEL2_MUX_CLK_NIC2X1_HCLK_MASK)



//switch

#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_EPP_APB_CLK_MASK                                                  (0xC0000000UL) /*bit[31:30] switch subsystem EPP APB interface clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_EPP_APB_CLK_SHIFT                                                 (30U)
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_EPP_APB_CLK(x)                                                    (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_EPP_APB_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_EPP_APB_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_EPP_AXI_CLK_MASK                                                  (0x30000000UL) /*bit[29:28] switch subsystem EPP AXI interface clock select 0: osc input 25Mhz clock 1: 800Mhz clock 2: 600Mhz clock 3: 400Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_EPP_AXI_CLK_SHIFT                                                 (28U)
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_EPP_AXI_CLK(x)                                                    (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_EPP_AXI_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_EPP_AXI_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_GMAC_APB_CLK_MASK                                                 (0x0C000000UL) /*bit[27:26] switch subsystem GMAC APB interface clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_GMAC_APB_CLK_SHIFT                                                (26U)
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_GMAC_APB_CLK(x)                                                   (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_GMAC_APB_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_GMAC_APB_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_GMAC_AXI_CLK_MASK                                                 (0x03000000UL) /*bit[25:24] switch subsystem GMAC AXI master interface clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_GMAC_AXI_CLK_SHIFT                                                (24U)
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_GMAC_AXI_CLK(x)                                                   (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_GMAC_AXI_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_GMAC_AXI_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_PPI2_CLK_MASK                                                  (0x00C00000UL) /*bit[23:22] switch subsystem R5 ppi2 clock select 0: osc input 25Mhz clock 1: 600Mhz clock 2: 400Mhz clock 3: 200Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_PPI2_CLK_SHIFT                                                 (22U)
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_PPI2_CLK(x)                                                    (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_PPI2_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_PPI2_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_PPI1_CLK_MASK                                                  (0x00300000UL) /*bit[21:20] switch subsystem R5 ppi1 clock select 0: osc input 25Mhz clock 1: 600Mhz clock 2: 400Mhz clock 3: 200Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_PPI1_CLK_SHIFT                                                 (20U)
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_PPI1_CLK(x)                                                    (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_PPI1_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_PPI1_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_PPI0_CLK_MASK                                                  (0x000C0000UL) /*bit[19:18] switch subsystem R5 ppi0 clock select 0: osc input 25Mhz clock 1: 600Mhz clock 2: 400Mhz clock 3: 200Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_PPI0_CLK_SHIFT                                                 (18U)
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_PPI0_CLK(x)                                                    (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_PPI0_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_PPI0_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_APB4_5_CLK_MASK                                                (0x00030000UL) /*bit[17:16] switch subsystem R5 APB4/5 clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_APB4_5_CLK_SHIFT                                               (16U)
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_APB4_5_CLK(x)                                                  (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_APB4_5_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_APB4_5_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_APB2_3_CLK_MASK                                                (0x0000C000UL) /*bit[15:14] switch subsystem R5 APB2/3 clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_APB2_3_CLK_SHIFT                                               (14U)
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_APB2_3_CLK(x)                                                  (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_APB2_3_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_APB2_3_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_APB0_1_CLK_MASK                                                (0x00003000UL) /*bit[13:12] switch subsystem R5 APB0/1 clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_APB0_1_CLK_SHIFT                                               (12U)
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_APB0_1_CLK(x)                                                  (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_APB0_1_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_APB0_1_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_NIC4_5_CLK_MASK                                                (0x00000C00UL) /*bit[11:10] switch subsystem R5 nic4/5 clock select 0: osc input 25Mhz clock 1: 600Mhz clock 2: 400Mhz clock 3: 200Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_NIC4_5_CLK_SHIFT                                               (10U)
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_NIC4_5_CLK(x)                                                  (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_NIC4_5_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_NIC4_5_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_NIC2_3_CLK_MASK                                                (0x00000300UL) /*bit[9:8] switch subsystem R5 nic2/3 clock select 0: osc input 25Mhz clock 1: 600Mhz clock 2: 400Mhz clock 3: 200Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_NIC2_3_CLK_SHIFT                                               (8U)
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_NIC2_3_CLK(x)                                                  (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_NIC2_3_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_NIC2_3_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_NIC0_1_CLK_MASK                                                (0x000000C0UL) /*bit[7:6] switch subsystem R5 nic0/1 clock select 0: osc input 25Mhz clock 1: 600Mhz clock 2: 400Mhz clock 3: 200Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_NIC0_1_CLK_SHIFT                                               (6U)
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_NIC0_1_CLK(x)                                                  (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_NIC0_1_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_NIC0_1_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_CORE4_5_CLK_MASK                                               (0x00000030UL) /*bit[5:4] switch subsystem R5 core4/5 clock select 0: osc input 25Mhz clock 1: 1200Mhz clock 2: 800Mhz clock 3: 400Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_CORE4_5_CLK_SHIFT                                              (4U)
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_CORE4_5_CLK(x)                                                 (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_CORE4_5_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_CORE4_5_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_CORE2_3_CLK_MASK                                               (0x0000000CUL) /*bit[3:2] switch subsystem R5 core2/3 clock select 0: osc input 25Mhz clock 1: 1200Mhz clock 2: 800Mhz clock 3: 400Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_CORE2_3_CLK_SHIFT                                              (2U)
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_CORE2_3_CLK(x)                                                 (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_CORE2_3_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_CORE2_3_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_CORE0_1_CLK_MASK                                               (0x00000003UL) /*bit[1:0] switch subsystem R5 core0/1 clock select 0: osc input 25Mhz clock 1: 1200Mhz clock 2: 800Mhz clock 3: 400Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_CORE0_1_CLK_SHIFT                                              (0U)
#define SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_CORE0_1_CLK(x)                                                 (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_CORE0_1_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL0_MUX_CLK_SW_R5_CORE0_1_CLK_MASK)


#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SDMA_AXI_CLK_MASK                                                 (0xC0000000UL) /*bit[31:30] switch subsystem sdma axi clock select 0: osc input 25Mhz clock 1: 400Mhz clock 2: 200Mhz clock 3: 100Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SDMA_AXI_CLK_SHIFT                                                (30U)
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SDMA_AXI_CLK(x)                                                   (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SDMA_AXI_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SDMA_AXI_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SDMA_CORE_CLK_MASK                                                (0x30000000UL) /*bit[29:28] switch subsystem sdma core clock select 0: osc input 25Mhz clock 1: 400Mhz clock 2: 200Mhz clock 3: 100Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SDMA_CORE_CLK_SHIFT                                               (28U)
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SDMA_CORE_CLK(x)                                                  (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SDMA_CORE_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SDMA_CORE_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SDMA_CFG_CLK_MASK                                                 (0x0C000000UL) /*bit[27:26] switch subsystem sdma configuration clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SDMA_CFG_CLK_SHIFT                                                (26U)
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SDMA_CFG_CLK(x)                                                   (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SDMA_CFG_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SDMA_CFG_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SYSCTRL_CSR_CLK_MASK                                              (0x03000000UL) /*bit[25:24] switch subsystem system control CSR apb clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SYSCTRL_CSR_CLK_SHIFT                                             (24U)
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SYSCTRL_CSR_CLK(x)                                                (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SYSCTRL_CSR_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SYSCTRL_CSR_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_FLEXRAY_AHB_NIC_BRIDGE_CLK_MASK                                   (0x00C00000UL) /*bit[23:22] switch subsystem flexray AHB nic bridge and bus clock select 0: osc input 25Mhz clock 1: 400Mhz clock 2: 200Mhz clock 3: 100Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_FLEXRAY_AHB_NIC_BRIDGE_CLK_SHIFT                                  (22U)
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_FLEXRAY_AHB_NIC_BRIDGE_CLK(x)                                     (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_FLEXRAY_AHB_NIC_BRIDGE_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_FLEXRAY_AHB_NIC_BRIDGE_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_STANDBY_SRAM_CLK_MASK                                             (0x00300000UL) /*bit[21:20] switch subsystem standby SRAM clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_STANDBY_SRAM_CLK_SHIFT                                            (20U)
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_STANDBY_SRAM_CLK(x)                                               (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_STANDBY_SRAM_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_STANDBY_SRAM_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SRAM1_CLK_MASK                                                    (0x000C0000UL) /*bit[19:18] switch subsystem SRAM1 clock select 0: osc input 25Mhz clock 1: 600Mhz clock 2: 400Mhz clock 3: 200Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SRAM1_CLK_SHIFT                                                   (18U)
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SRAM1_CLK(x)                                                      (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SRAM1_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SRAM1_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SRAM0_CLK_MASK                                                    (0x00030000UL) /*bit[17:16] switch subsystem SRAM0 clock select 0: osc input 25Mhz clock 1: 600Mhz clock 2: 400Mhz clock 3: 200Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SRAM0_CLK_SHIFT                                                   (16U)
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SRAM0_CLK(x)                                                      (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SRAM0_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SRAM0_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_DMA_CLK_MASK                                                      (0x0000C000UL) /*bit[15:14] switch subsystem DMA clock select 0: osc input 25Mhz clock 1: 400Mhz clock 2: 200Mhz clock 3: 100Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_DMA_CLK_SHIFT                                                     (14U)
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_DMA_CLK(x)                                                        (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_DMA_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_DMA_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SECURITY_ACCELERATION_CLK_MASK                                    (0x00003000UL) /*bit[13:12] switch subsystem security acceleration config clock select 0: osc input 25Mhz clock 1: 600Mhz clock 2: 400Mhz clock 3: 200Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SECURITY_ACCELERATION_CLK_SHIFT                                   (12U)
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SECURITY_ACCELERATION_CLK(x)                                      (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SECURITY_ACCELERATION_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SECURITY_ACCELERATION_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SECURITY_ACCELERATION_AXI_CLK_MASK                                (0x00000C00UL) /*bit[11:10] switch subsystem security acceleration axi clock select 0: osc input 25Mhz clock 1: 600Mhz clock 2: 400Mhz clock 3: 200Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SECURITY_ACCELERATION_AXI_CLK_SHIFT                               (10U)
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SECURITY_ACCELERATION_AXI_CLK(x)                                  (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SECURITY_ACCELERATION_AXI_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_SECURITY_ACCELERATION_AXI_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_FLEXRAY_AHB_CLK_MASK                                          (0x00000300UL) /*bit[9:8] switch subsystem LSP flex ray ahb clock select 0: osc input 25Mhz clock 1: 200Mhz clock(from divider)  2: 100Mhz clock 3: 50Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_FLEXRAY_AHB_CLK_SHIFT                                         (8U)
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_FLEXRAY_AHB_CLK(x)                                            (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_FLEXRAY_AHB_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_FLEXRAY_AHB_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_CAN_WORK_CLK_MASK                                             (0x000000C0UL) /*bit[7:6] switch subsystem LSP CAN work clock select 0: osc input 25Mhz clock 1: 400Mhz clock 2: 200Mhz clock 3: 100Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_CAN_WORK_CLK_SHIFT                                            (6U)
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_CAN_WORK_CLK(x)                                               (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_CAN_WORK_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_CAN_WORK_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_WORK_CLK_MASK                                                 (0x00000030UL) /*bit[5:4] switch subsystem LSP work clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_WORK_CLK_SHIFT                                                (4U)
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_WORK_CLK(x)                                                   (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_WORK_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_WORK_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_CAN_APB_CLK_MASK                                              (0x0000000CUL) /*bit[3:2] switch subsystem LSP CAN APB clock select 0: osc input 25Mhz clock 1: 600Mhz clock 2: 400Mhz clock 3: 200Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_CAN_APB_CLK_SHIFT                                             (2U)
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_CAN_APB_CLK(x)                                                (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_CAN_APB_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_CAN_APB_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_PCS_APB_CLK_MASK                                              (0x00000003UL) /*bit[1:0] switch subsystem PCS APB interface clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_PCS_APB_CLK_SHIFT                                             (0U)
#define SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_PCS_APB_CLK(x)                                                (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_PCS_APB_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL1_MUX_CLK_SW_LSP_PCS_APB_CLK_MASK)



#define SW_CRM_CSR_SW_CLK_SEL2_MUX_CLK_SW_PTP_CLK_SEL_MASK                                                  (0x00004000UL) /*bit[6] 0: OSC input clock 25Mhz 1: ptp_div_clk*/
#define SW_CRM_CSR_SW_CLK_SEL2_MUX_CLK_SW_PTP_CLK_SEL_SHIFT                                                 (14U)
#define SW_CRM_CSR_SW_CLK_SEL2_MUX_CLK_SW_PTP_CLK_SEL(x)                                                    (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL2_MUX_CLK_SW_PTP_CLK_SEL_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL2_MUX_CLK_SW_PTP_CLK_SEL_MASK)

#define SW_CRM_CSR_SW_CLK_SEL2_MUX_CLK_SW_PTP_CLK_SEL_PTP_DIV_CLK_MASK                                      (0x00003000UL) /*bit[5:4] ptp_div_clk divider select 2'b00: ptp_mux_clk 2'b01: ptp_mux_clk/2 2'b10: ptp_mux_clk/4 2'b11: ptp_mux_clk/5*/
#define SW_CRM_CSR_SW_CLK_SEL2_MUX_CLK_SW_PTP_CLK_SEL_PTP_DIV_CLK_SHIFT                                     (12U)
#define SW_CRM_CSR_SW_CLK_SEL2_MUX_CLK_SW_PTP_CLK_SEL_PTP_DIV_CLK(x)                                        (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL2_MUX_CLK_SW_PTP_CLK_SEL_PTP_DIV_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL2_MUX_CLK_SW_PTP_CLK_SEL_PTP_DIV_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL2_MUX_CLK_SW_PTP_CLK_SEL_PTP_MUX_CLK_MASK                                      (0x00000F00UL) /*bit[3:0] ptp_mux_clk select 4'b0xxx: input clock pad ptp_clk 4'b1000: ethernet external port0 MAC receive clock 4'b1000: ethernet external port1 MAC receive clock 4'b1000: ethernet external port2 MAC receive clock 4'b1000: ethernet external port3 MAC receive clock 4'b110x: PLL ETH ouput 125M clock,divide from FOUT[3] 4'b1110: PLL ETH ouput 125M clock,divide from FOUT[3] 4'b1111: safety subsystem exteranl GMAC receive clock*/
#define SW_CRM_CSR_SW_CLK_SEL2_MUX_CLK_SW_PTP_CLK_SEL_PTP_MUX_CLK_SHIFT                                     (8U)
#define SW_CRM_CSR_SW_CLK_SEL2_MUX_CLK_SW_PTP_CLK_SEL_PTP_MUX_CLK(x)                                        (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL2_MUX_CLK_SW_PTP_CLK_SEL_PTP_MUX_CLK_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL2_MUX_CLK_SW_PTP_CLK_SEL_PTP_MUX_CLK_MASK)

#define SW_CRM_CSR_SW_CLK_SEL2_APBSW_CLK_SEL_MASK                                                           (0x00000030UL) /*switch subsystem APB bus switch and lsp apb clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL2_APBSW_CLK_SEL_SHIFT                                                          (4U)
#define SW_CRM_CSR_SW_CLK_SEL2_APBSW_CLK_SEL(x)                                                             (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL2_APBSW_CLK_SEL_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL2_APBSW_CLK_SEL_MASK)

#define SW_CRM_CSR_SW_CLK_SEL2_NOC_CLK_SEL_MASK                                                             (0x0000000CUL) /*switch subsystem NOC clock select 0: osc input 25Mhz clock 1: 600Mhz clock 2: 400Mhz clock 3: 200Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL2_NOC_CLK_SEL_SHIFT                                                            (2U)
#define SW_CRM_CSR_SW_CLK_SEL2_NOC_CLK_SEL(x)                                                               (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL2_NOC_CLK_SEL_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL2_NOC_CLK_SEL_MASK)

#define SW_CRM_CSR_SW_CLK_SEL2_CRM_CLK_SEL_MASK                                                             (0x00000003UL) /*switch subsystem CRM csr clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock*/
#define SW_CRM_CSR_SW_CLK_SEL2_CRM_CLK_SEL_SHIFT                                                            (0U)
#define SW_CRM_CSR_SW_CLK_SEL2_CRM_CLK_SEL(x)                                                               (((uint32_t)(((uint32_t)(x)) << SW_CRM_CSR_SW_CLK_SEL2_CRM_CLK_SEL_SHIFT)) & SW_CRM_CSR_SW_CLK_SEL2_CRM_CLK_SEL_MASK)



void Mcu_Bst_InitClock(void);


#endif